VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture Using Clock Gating

This paper proposes the VLSI implementation of a fully parallel and Canonical Signed Digit (CSD)-based FIR filter architecture, focusing on achieving area and power optimization. The optimization is achieved by incorporating a Vedic multiplier and a Kogge- Computational efficiency is greatly increased by using a stone adder rather than conventional multipliers and adders. Synthesis-based clock gating, which minimizes needless switching activity by dynamically disabling the clock signal for idle components, is used to further reduce power usage. An accurate comparison of the proposed architecture is performed for 8-tap FIR filters in both linear and tree topologies to evaluate performance trade-offs. Additionally, the architecture is analyzed under a pipelined mechanism to improve throughput while maintaining low power consumption. The VLSI implementation is carried out using Verilog HDL and synthesized in Xilinx Vivado 2018.3, showcasing the feasibility of the design for high-performance and energy-efficient signal processing applications.