High Throughput DWT Architecture for Signal Processing

The Discrete Wavelet Transform (DWT) is essential in signal processing systems because it is capable of accurately recording both frequency and time-domain features. Nevertheless, the computational intricacy of DWT presents notable obstacles to processing in real-time, particularly in circumstances with large data consumption. This study presents a VLSI technology designed to accelerate DWT processing utilizing CMOS gates. The goal is to improve throughput while maintaining area efficiency. The architecture utilizes parallelism and pipelining techniques to take use of the fundamental redundancy in DWT processing. We focus on creating customized processing units developed specifically for performing Discrete Wavelet Transform (DWT) operations. These units are tuned to make the best possible usage of CMOS gate capabilities. The proposed architectural is implemented using Cadence virtuoso software with 45 nm design. It is evaluated based on its area, power consumption, and latency. The current techniques employed to assess the proposed design include the utilization of the Radix-2 technique for FIR filter design, as well as the employment of look-up-table carry select adder (LCSLA), Vedic design (VD), and carry look-ahead adder (CLA). The developed system design has an area of 1764 um2, which makes it smaller than that of conventional approaches.