Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter

This paper proposes the design, implementation, and verification of a vending machine using the Finite State Machine (FSM) methodology in Verilog HDL. The FSM is used to manage the multiple states of the vending machine, including “idle,” “accepting coins,” “dispensing item,” and “returning change.” The implementation of the vending machine is done in Verilog HDL, and the FSM is implemented as a state diagram. The design is then synthesized using the Genus synthesis tool and implemented using the Encounter implementation tool. The Genus tool uses advanced optimization techniques, such as timing-driven placement and clock tree synthesis, to improve the design’s performance and area. The Encounter tool performs physical design, including placement and routing, to meet the design’s timing, power, and area constraints. To validate the design’s correctness and functionality, a test bench is created to simulate the behavior of the vending machine. The simulation results are then used to verify that the design meets the required specifications and that the FSM behaves as expected. The proposed design is then can be implemented on a Field Programmable Gate Array (FPGA) to demonstrate its effectiveness in a real-world scenario. The results of the implementation are presented and analyzed to validate the design’s performance, power consumption, and area. Overall, the vending machine using FSM in Verilog HDL, implemented in Genus and Encounter, provides a reliable and efficient solution for users to purchase items from the machine. The proposed design and implementation demonstrate the feasibility and effectiveness of this approach, and the results show that the design meets the required specifications and performs well in a real-world scenario.