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RTL to GDS-II Implementation of a RISC-V RAM Design

Author

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  • M Sohana.

    (Dept. of Electronics & Communication Engineering University College of Engineering & Technology, Acharya Nagarjuna University Guntur, Andhra Pradesh, India – 522510)

  • Dr. P. Dhanalakshmi

    (Dept. of Electronics & Communication Engineering University College of Engineering & Technology, Acharya Nagarjuna University Guntur, Andhra Pradesh, India – 522510)

Abstract

This paper presents a complete ASIC design flow for a RISC-V based 16×8 RAM module, spanning the full pipeline from Register Transfer Level (RTL) coding in Verilog to GDS-II physical layout generation. The RAM is functionally verified using Cadence Xcelium, synthesized using Synopsys Design Compiler, and carried through floor planning, placement, Clock Tree Synthesis (CTS), and routing using Cadence Innovus. Physical sign-off via Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Static Timing Analysis (STA) yields a tape-out-ready GDS-II file. Benchmarking against the ARM Cortex-A5 in TSMC 40GPLUS demonstrates 48% area reduction, 57% lower dynamic power, and 9.5% higher Dhrystone performance. Fault-tolerance analysis further evaluates TMR and Hamming ECC overhead, establishing design guidelines for radiation-critical VLSI applications.

Suggested Citation

  • M Sohana. & Dr. P. Dhanalakshmi, 2026. "RTL to GDS-II Implementation of a RISC-V RAM Design," International Journal of Research and Innovation in Applied Science, International Journal of Research and Innovation in Applied Science (IJRIAS), vol. 11(6), pages 2338-2345, June.
    • Handle: RePEc:bjf:journl:v:11:y:2026:i:6:p:2338-2345
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