Design of Modified Dual-CLCG Algorithm for Pseudo-Random Bit Generator

Pseudorandom bit generators (PRBGs) are indispensable in modern cryptography, forming the backbone of secure communication protocols, authentication mechanisms, and privacy-preserving systems. A PRBG must produce sequences that appear statistically random while being computationally unpredictable. Traditional designs such as linear feedback shift registers (LFSR) and linear congruential generators (LCG) are attractive due to their simplicity and low hardware cost, but they fail several National Institute of Standards and Technology (NIST) randomness tests because of inherent linearity. Coupled LCG (CLCG) and dual-CLCG methods improve resilience by combining multiple generators, but they suffer from irregular timing, high latency, and excessive hardware usage. This paper proposes a modified dual-CLCG algorithm and its VLSI architecture designed to produce pseudorandom bits at a consistent clock rate with minimal hardware overhead. The novelty lies in the use of a simplified XOR stage at the output, which ensures uniform bit generation at every clock cycle. Unlike the dual-CLCG, which requires multiple flip-flops and suffers from asynchronous bit release, the modified design achieves a maximum sequence length of 2^n, requires only one initial delay cycle, and passes all fifteen NIST benchmark tests. The architecture was implemented using Verilog HDL and prototyped on FPGA hardware. Experimental results demonstrate significant improvements in area efficiency, latency reduction, and power consumption compared to existing designs. The proposed generator not only meets the randomness requirements but also achieves polynomial-time unpredictability, making it suitable for resource-constrained IoT devices where lightweight cryptographic primitives are essential.