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Optimized 2/3 Prescaler Design Using Different Logic Families in 45nm CMOS Process

Author

Listed:
  • G. Vimala

    (Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Tambaram, Chennai)

  • F. Vincy Lloyd

    (Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Tambaram, Chennai)

Abstract

Frequency division is a key application of flip-flops, particularly in wideband frequency synthesizers based on phase-locked loops (PLLs). In such systems, the high-frequency output from the voltage-controlled oscillator (VCO) is typically fed directly into a prescaler, also known as an N/N+1 counter, which serves as a critical building block. As semiconductor technology continues to scale down, both the channel length and supply voltage are significantly reduced. Consequently, the prescaler must operate reliably at higher frequencies and under lower voltage conditions.

Suggested Citation

  • G. Vimala & F. Vincy Lloyd, 2025. "Optimized 2/3 Prescaler Design Using Different Logic Families in 45nm CMOS Process," International Journal of Latest Technology in Engineering, Management & Applied Science, RSIS International, vol. 14(8), pages 361-364, August.
    • Handle: RePEc:bjf:ijltem:v:14:y:2025:i:8:a:1619
    DOI: 10.51583/IJLTEMAS.2025.1408000043
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