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A Novel High Performance Architecture for Mac Unit Using Vedic Multiplier and Brent-Kung Adder

Author

Listed:
  • M.S.N.V. Mohith.

    (Department of Electronics and Communication Engineering, India)

  • Dr. S. Ravi

    (Department of Electronics and Communication Engineering, India)

  • K. Yaswanth Simha

    (Department of Electronics and Communication Engineering, India)

  • L. Alekhya.

    (Department of Electronics and Communication Engineering, India)

  • M. Maruthi Sriram

    (Department of Electronics and Communication Engineering, India)

Abstract

The DSP industries make use of Multiply and Accumulate (MAC) units in their systems unanimously. As the name implies, MAC unit performs both Multiplication and addition operations. The proposed MAC unit make use of parallel prefix adder, instead of ripple carry adder, and hence there is an improvement in the performance of the DSP processors. Further, this paper also examines the performance by using Brent-Kung adder, one of the high-speed adders which is used to reduce the delay of MAC units. To enhance the performance of multiplication process, the proposed design uses a Vedic multiplier, based on Urdhva Tiryagbhyam (UT) sutra. Verilog HDL is used to do the analysis of the MAC unit and Xilinx ISE 14.7 is used to simulate and synthesis the MAC unit.

Suggested Citation

  • M.S.N.V. Mohith. & Dr. S. Ravi & K. Yaswanth Simha & L. Alekhya. & M. Maruthi Sriram, 2025. "A Novel High Performance Architecture for Mac Unit Using Vedic Multiplier and Brent-Kung Adder," International Journal of Research and Scientific Innovation, International Journal of Research and Scientific Innovation (IJRSI), vol. 12(4), pages 202-210, April.
    • Handle: RePEc:bjc:journl:v:12:y:2025:i:4:p:202-210
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