Author
Abstract
In diamond wire sawing (DWS) of photovoltaic silicon wafers, total thickness variation (TTV) and micro-cracks are difficult to predict online, and process optimization still depends largely on trial and error. This study takes the silicon wafer DWS dataset (solar_raw for experiments, solar_sim for simulation) officially released by the "Lightweight Design and AI Application" track of the national final of the 19th "Gaojiao Cup" National Undergraduate Advanced Graphics Technology and Product Information Modeling Innovation Contest, and carries out cleaning, merging, training, evaluation, and reverse optimization on the Simcenter AI Studio 2025.0.1 platform. Cleaning leaves 141 experimental samples and 152 simulation samples, from which an inner join yields 62 merged samples. On the 62-row merged table, Linear Regression (OLS) in AI Studio reaches a test-set RMSE of 2.775 μm (relative error 9.08%) under a 70/30 split, and the Model Simulator predicts TTV=19.956 μm for a given set of process inputs. A separate Python re-computation (scikit-learn/xgboost, 5-fold cross-validation, 7 regression models) on the 141-row experimental table again finds OLS the most accurate (RMSE=1.136 μm, R2=0.907), with feed_rate the dominant factor for TTV (r=+0.706); for micro-crack classification, Logistic Regression (LogReg) performs best (F1=0.527, AUC=0.816). A multi-fidelity ablation shows that adding finite-element simulation features (wire stress/deflection) does not improve prediction accuracy for this dataset under the small-sample condition. Reverse optimization on the platform (Find Optimal Input Settings, with three modes Specific Value / Minimize / Maximize) and on the Python side (Ridge surrogate + RF-crack-probability ε-constraint) both recommend the same low-TTV, low-crack process window; the platform's Top1 falls within the Python top-3, and the Top1 window cuts the predicted TTV by about 43.5% relative to the experimental-table mean. The results suggest that a no-code AutoML platform is a practical option for silicon wafer sawing process optimization.
Suggested Citation
Download full text from publisher
Corrections
All material on this site has been provided by the respective publishers and authors. You can help correct errors and omissions. When requesting a correction, please mention this item's handle: RePEc:axf:aidtaa:v:3:y:2026:i:3:p:32-40. See general information about how to correct material in RePEc.
If you have authored this item and are not yet registered with RePEc, we encourage you to do it here. This allows to link your profile to this item. It also allows you to accept potential citations to this item that we are uncertain about.
We have no bibliographic references for this item. You can help adding them by using this form .
If you know of missing items citing this one, you can help us creating those links by adding the relevant references in the same way as above, for each refering item. If you are a registered author of this item, you may also want to check the "citations" tab in your RePEc Author Service profile, as there may be some citations waiting for confirmation.
For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: Yuchi Liu (email available below). General contact details of provider: https://soapubs.com/index.php/ICSS .
Please note that corrections may take a couple of weeks to filter through
the various RePEc services.