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On approach to increasing the density of field-effect heterotransistors in the framework of a level shifter: Influence of mismatch-induced stress and porosity of materials on the technological process

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  • Evgeny Leonidovich Pankratov

Abstract

In this paper, we introduce an approach to increase the density of field-effect heterotransistors in the framework of a level shifter. In the framework of the approach, we consider the manufacturing of the inverter in a heterostructure with a specific configuration. Several required areas of the heterostructure should be doped by diffusion or ion implantation to the required types of conductivity (p or n) to manufacture the recently described transistors. After that, dopants and radiation defects should be annealed in the framework of an optimized scheme. The optimized scheme leads to obtaining a maximal compromise between increasing the homogeneity of the concentration of dopants in the enriched area and increasing the speed of the decrease of dopant concentration after the enriched area. We also analyzed the influence of the porosity of materials of the heterostructure and mismatch-induced stress near the interfaces of the heterostructure on the technological process. At the same time, we consider an approach to decrease the value of mismatch-induced stress in the considered heterostructure. We present an analytical approach to analyze mass and heat transport in heterostructures during the manufacturing of integrated circuits with account for mismatch-induced stress. The approach gives the possibility to take into account spatial and temporal variations of the considered technological process at one time, as well as the nonlinearity of the appropriate processes.

Suggested Citation

  • Evgeny Leonidovich Pankratov, 2025. "On approach to increasing the density of field-effect heterotransistors in the framework of a level shifter: Influence of mismatch-induced stress and porosity of materials on the technological process," International Journal of Modern Research in Electrical and Electronic Engineering, Asian Online Journal Publishing Group, vol. 9(1), pages 1-23.
  • Handle: RePEc:aoj:ijmree:v:9:y:2025:i:1:p:1-23:id:6506
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