Smashing OpenFlow's “atomic” actions: Programmable data plane packet manipulation in hardware

Recently, with new hardware architectures such as Reconfigurable Match Tables and languages such as P4, the Software Defined Networking community has started to bring line‐rate data plane programmability inside switching chipsets. Starting from the original OpenFlow's match/action abstraction, most of the work has so far focused on key improvements in matching flexibility. Conversely, the “action part,” ie, the set of operations (such as encapsulation or header manipulation) performed on packets after the forwarding decision, has received way less attention. Goal of this paper is to move beyond the idea of “atomic,” preimplemented, actions, and rather make them programmable while retaining high speed multi‐Gbps operation. To this purpose, we propose a domain‐specific HW architecture, called Packet Manipulation Processor (PMP), able to efficiently implement such actions. Both a PMP C++ instruction set simulator and a NetFPGA prototype have been developed. The performances of the PMP have been verified with three nontrivial use cases (tunneling, NAT, and ARP reply generation), showing that also in the worst case the throughput is well above 10 Gbps.