Estimating Spurious Power While Mapping K-Lut-Based Fpga Circuits
AbstractIn this paper is presented a new approach for decreasing the spurious power consumption in K-LUT based FPGA implemented circuits. The approach is based on selective collapsing nodes in a direct acyclic graph (DAG) representing combinational or synchronous sequential circuits. It was used the simulation-based approach that estimates, using Monte Carlo experiment, the spurious switching activity of each net in the circuit. Traversing circuits in topological order, step by step best K-feasible cone are computed at the output of each node. Preserving the best depth of the circuits the mapping stage is done searching to minimize spurious switching power.
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Bibliographic InfoArticle provided by Romanian-American University in its journal Journal of Information Systems and Operations Management.
Volume (Year): 3 (2009)
Issue (Month): 2 (December)
spurious switching power; K-feasible cones; optimum depth; optimal area and power;
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