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Optimizing Large Combinational Networks For K-Lut Based Fpga Mapping

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Author Info

  • Ion I. BUCUR

    (University Politehnica of Bucharest)

  • Ioana FĂGĂRĂŞAN

    (University Politehnica of Bucharest)

  • Cornel POPESCU

    (University Politehnica of Bucharest)

  • George CULEA

    (University of Bacǎu, Faculty of Electrical Engineering)

  • Alexandru E. ŞUŞU

    (Swiss Federal Institute of Technology Lausanne)

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    Abstract

    Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packages

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    File URL: http://www.rebe.rau.ro/RePEc/rau/jisomg/SU08/JISOM-SU08-A15.pdf
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    Bibliographic Info

    Article provided by Romanian-American University in its journal Journal of Information Systems and Operation Management.

    Volume (Year): 2 (2008)
    Issue (Month): 1 (July)
    Pages: 154-165

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    Handle: RePEc:rau:jisomg:v:2:y:2008:i:1:p:154-165

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    Related research

    Keywords: two-way partitioning; multi-way partitioning; recursive partitioning; flat partitioning; critical path; cutting cones; bottom-up clusters; top-down min-cut;

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