Optimizing Large Combinational Networks For K-Lut Based Fpga Mapping
AbstractOptimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packages
Download InfoIf you experience problems downloading a file, check if you have the proper application to view it first. In case of further problems read the IDEAS help page. Note that these files are not on the IDEAS site. Please be patient as the files may be large.
Bibliographic InfoArticle provided by Romanian-American University in its journal Journal of Information Systems and Operation Management.
Volume (Year): 2 (2008)
Issue (Month): 1 (July)
two-way partitioning; multi-way partitioning; recursive partitioning; flat partitioning; critical path; cutting cones; bottom-up clusters; top-down min-cut;
You can help add them by filling out this form.
reading list or among the top items on IDEAS.Access and download statisticsgeneral information about how to correct material in RePEc.
For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: (Alex Tabusca).
If references are entirely missing, you can add them using this form.