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Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process

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  • J-G Kim

    (University of Incheon, Incheon, Korea)

  • S-K Lim

    (Sungkyul University, Gyeonggi-do, Korea)

Abstract

We consider a problem of order-lot pegging in semiconductor wafer fabrication process. In the problem, we determine an assignment of wafers in lots to orders and a plan for input release of wafers into a wafer fabrication facility with the objective of minimizing total tardiness of the orders over a finite time horizon. The problem is formulated as a mixed integer linear program and proved to be strongly NP-hard. We find properties for an optimal order-lot assignment of the problem and develop a pegging method based on the properties. Also, we prove that an optimal order-lot assignment can be obtained by finding an optimal order sequence of assigning wafers to orders when using the pegging method developed in this study. In addition, we suggest two search heuristic algorithms for finding the optimal order sequence of assigning wafers to orders. The test results on randomly generated problems show that the suggested algorithms work fairly well compared to the commercial optimization software package and solve industrial-sized problems in a reasonable amount of time.

Suggested Citation

  • J-G Kim & S-K Lim, 2012. "Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process," Journal of the Operational Research Society, Palgrave Macmillan;The OR Society, vol. 63(9), pages 1258-1270, September.
    • Handle: RePEc:pal:jorsoc:v:63:y:2012:i:9:p:1258-1270
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