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An FPGA-Based Reconfigurable FIR Filter for SDR Applications

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  • Lincoln Alexandre Paz Silva

    (Federal University of Semiarid Region, Brazil)

  • Francisco de Assis Brito-Filho

    (Federal University of Semiarid Region, Brazil)

Abstract

This article presents a proposal of a reconfigurable FIR filter capable of covering the most common wireless communication standards on software-defined radio applications. The filter was implemented using a low-cost field programmable gate array, Cyclone IV EP4CE22F17C6 model from Altera®. System design is presented together with simulation results. Validation is done for a 500 kHz base-band noisy signal. The synthesized design uses 5,259 logic elements of which 4,778 were used for combinational logic blocks and 513 for dedicated logic registers, which represents 22% of total used FPGA capacity. The maximum sampling frequency supported by the architecture is 23.24 MHz.

Suggested Citation

  • Lincoln Alexandre Paz Silva & Francisco de Assis Brito-Filho, 2022. "An FPGA-Based Reconfigurable FIR Filter for SDR Applications," International Journal of Interdisciplinary Telecommunications and Networking (IJITN), IGI Global, vol. 14(1), pages 1-8, January.
    • Handle: RePEc:igg:jitn00:v:14:y:2022:i:1:p:1-8
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