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Simulation of a Low-Voltage Direct Current System Using T-SFCL to Enhance Low Voltage Ride through Capability

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Listed:
  • Kwang-Hoon Yoon

    (Department of Electrical Engineering, Soongsil University, 369, Sangdo-ro, Dongjak-gu, Seoul 06978, Korea)

  • Joong-Woo Shin

    (Department of Electrical Engineering, Soongsil University, 369, Sangdo-ro, Dongjak-gu, Seoul 06978, Korea)

  • Jae-Chul Kim

    (Department of Electrical Engineering, Soongsil University, 369, Sangdo-ro, Dongjak-gu, Seoul 06978, Korea)

  • Hyeong-Jin Lee

    (Korea Electric Power Research Institute (KEPRI), Korea Electric Power Company (KEPCO), 105, Munji-ro, Yuseong-gu, Daejeon 34056, Korea)

  • Jin-Seok Kim

    (Department of Electrical Engineering, Osan University, 45, Cheonghak-ro, Osan-si 18119, Korea)

Abstract

Owing to the increasing penetration level of distributed energy resources (DER) and direct current (DC) load, the usage of low-voltage direct current (LVDC) systems has expanded to achieve efficient operations. However, because the LVDC system reaches the peak fault current at a faster rate than the alternating current (AC) system, a solution that protects the system components is necessary to maintain system integrity. It is required by the low-voltage ride-through (LVRT) that the DERs maintain their interconnections with the LVDC system and support fault recovery. In this study, a method is proposed to allow the application of the superconducting fault current limiter (SFCL) to reduce the fault current and enhance the LVRT capability. However, when the DER maintain a connection to support fault recovery, the conventional resistive-type SFCL must withstand the burden of high-temperature superconducting (HTSC) operation during fault state dependence on LVRT. Therefore, this study proposes a trigger-type SFCL to reduce the burden of the HTSC element and enhance the LVRT capability. The voltage sag related to the LVRT was improved owing to the SFCL. The proposed solution was confirmed using PSCAD/EMTDC, which is a commercial software.

Suggested Citation

  • Kwang-Hoon Yoon & Joong-Woo Shin & Jae-Chul Kim & Hyeong-Jin Lee & Jin-Seok Kim, 2022. "Simulation of a Low-Voltage Direct Current System Using T-SFCL to Enhance Low Voltage Ride through Capability," Energies, MDPI, vol. 15(6), pages 1-11, March.
    • Handle: RePEc:gam:jeners:v:15:y:2022:i:6:p:2111-:d:770690
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    References listed on IDEAS

    as
    1. Navid Bayati & Hamid Reza Baghaee & Mehdi Savaghebi & Amin Hajizadeh & Mohsen N. Soltani & Zhengyu Lin, 2021. "DC Fault Current Analyzing, Limiting, and Clearing in DC Microgrid Clusters," Energies, MDPI, vol. 14(19), pages 1-19, October.
    2. Jae-In Lee & Van Quan Dao & Minh-Chau Dinh & Seok-ju Lee & Chang Soon Kim & Minwon Park, 2021. "Combined Operation Analysis of a Saturated Iron-Core Superconducting Fault Current Limiter and Circuit Breaker for an HVDC System Protection," Energies, MDPI, vol. 14(23), pages 1-18, November.
    3. Hyeong-Jin Lee & Sung-Hun Lim & Jae-Chul Kim, 2019. "Application of a Superconducting Fault Current Limiter to Enhance the Low-Voltage Ride-Through Capability of Wind Turbine Generators," Energies, MDPI, vol. 12(8), pages 1-14, April.
    4. Lei Chen & Xiude Tu & Hongkun Chen & Jun Yang & Yayi Wu & Xin Shu & Li Ren, 2016. "Technical Evaluation of Superconducting Fault Current Limiters Used in a Micro-Grid by Considering the Fault Characteristics of Distributed Generation, Energy Storage and Power Loads," Energies, MDPI, vol. 9(10), pages 1-21, September.
    5. Van Quan Dao & Jae-In Lee & Chang Soon Kim & Minwon Park & Umberto Melaccio, 2020. "Design and Performance Analysis of a Saturated Iron-Core Superconducting Fault Current Limiter for DC Power Systems," Energies, MDPI, vol. 13(22), pages 1-18, November.
    6. Haipeng Jia & Jingyuan Yin & Tongzhen Wei & Qunhai Huo & Jinke Li & Lixin Wu, 2020. "Short-Circuit Fault Current Calculation Method for the Multi-Terminal DC Grid Considering the DC Circuit Breaker," Energies, MDPI, vol. 13(6), pages 1-23, March.
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