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A comparison of Fault Trees and the Dynamic Flowgraph Methodology for the analysis of FPGA-based safety systems Part 1: Reactor trip logic loop reliability analysis

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  • McNelles, Phillip
  • Zeng, Zhao Chang
  • Renganathan, Guna
  • Lamarre, Greg
  • Akl, Yolande
  • Lu, Lixuan

Abstract

The use of Field Programmable Gate Arrays (FPGAs) in safety critical systems in nuclear power plants means that these systems must undergo a detailed reliability and safety analysis. Fault Tree Analysis (FTA) has seen extensive use in the nuclear power industry. However, FTA predates digital I&C systems, and only performs static analyses. Therefore, dynamic (time dependent) methodologies have been created to model and analyze digital I&C systems. One method is the Dynamic Flowgraph Methodology (DFM). DFM can model control loops and feedback, which are properties that FPGA-based systems include. This work presents a comparison of FTA and DFM analysis methods, for analyzing the reliability of a generic, one-parameter, one-channel FPGA-based reactor trip logic loop. The system was analyzed for two separate failure conditions, with the DFM and FTA results being compared. The DFM and FTA results were similar for simple systems using one time step, however the results were more different for multiple time steps and/or complex test systems. Issues with FTA were discovered pertaining to the oscillating clock states, leading to impossible MCS being returned by the FTA. Potential reasons for the different results returned by two methods are discussed, as is direction for future comparisons between these methods.

Suggested Citation

  • McNelles, Phillip & Zeng, Zhao Chang & Renganathan, Guna & Lamarre, Greg & Akl, Yolande & Lu, Lixuan, 2016. "A comparison of Fault Trees and the Dynamic Flowgraph Methodology for the analysis of FPGA-based safety systems Part 1: Reactor trip logic loop reliability analysis," Reliability Engineering and System Safety, Elsevier, vol. 153(C), pages 135-150.
    • Handle: RePEc:eee:reensy:v:153:y:2016:i:c:p:135-150
    DOI: 10.1016/j.ress.2016.04.014
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    1. Aldemir, T. & Guarro, S. & Mandelli, D. & Kirschenbaum, J. & Mangan, L.A. & Bucci, P. & Yau, M. & Ekici, E. & Miller, D.W. & Sun, X. & Arndt, S.A., 2010. "Probabilistic risk assessment modeling of digital instrumentation and control systems using two dynamic methodologies," Reliability Engineering and System Safety, Elsevier, vol. 95(10), pages 1011-1039.
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    4. Ilkka Karanta, 2013. "Implementing dynamic flowgraph methodology models with logic programs," Journal of Risk and Reliability, , vol. 227(3), pages 302-314, June.
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    Cited by:

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    2. McNelles, Phillip & Renganathan, Guna & Zeng, Zhao Chang & Chirila, Marius & Lu, Lixuan, 2019. "A comparison of fault trees and the Dynamic Flowgraph Methodology for the analysis of FPGA-based safety systems part 2: Theoretical investigations," Reliability Engineering and System Safety, Elsevier, vol. 183(C), pages 60-83.
    3. Villalta, Igor & Bidarte, Unai & Gómez-Cornejo, Julen & Jiménez, Jaime & Lázaro, Jesús, 2018. "SEU emulation in industrial SoCs combining microprocessor and FPGA," Reliability Engineering and System Safety, Elsevier, vol. 170(C), pages 53-63.
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    5. Zio, E., 2018. "The future of risk assessment," Reliability Engineering and System Safety, Elsevier, vol. 177(C), pages 176-190.
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    8. Jung, Sejin & Yoo, Junbeom & Lee, Young-Jun, 2020. "A practical application of NUREG/CR-6430 software safety hazard analysis to FPGA software," Reliability Engineering and System Safety, Elsevier, vol. 202(C).

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