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Optimal Area And Performance Mapping Of K-Lut Based Fpgas

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Author Info

  • Ion I. BUCUR

    (University Politehnica of Bucharest)

  • Cornel POPESCU

    (University Politehnica of Bucharest)

  • George CULEA

    (University of Bacǎu)

  • Alexandru E. ŞUŞU

    (Swiss Federal Institute of Technology Lausanne)

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    Abstract

    FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map, both for area and performance, combinational networks using k-LUT based FPGAs.

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    File URL: http://www.rebe.rau.ro/RePEc/rau/jisomg/FA08/JISOM-FA08-A5.pdf
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    Bibliographic Info

    Article provided by Romanian-American University in its journal Journal of Information Systems and Operation Management.

    Volume (Year): 2 (2008)
    Issue (Month): 2 (November)
    Pages: 375-390

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    Handle: RePEc:rau:jisomg:v:2:y:2008:i:2:p:375-390

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    Keywords: k-LUT based FPGAs; combinational circuits; performance-driven mapping.;

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